Sensors & Transducers Journal
(ISSN 1726- 5479)
Vol. 80, Issue 6, June 2007, pp. 1257-1263
Interconnect-Induced Effects on High-Speed Submicron ADC and Clocking Scheme
Faculty of ECE, University of Tehran, Iran
PO Box 14395-413, Tehran, Iran
Tel.: +98 21 44668606, E-mail: firstname.lastname@example.org
Received: 10 May 2007 /Accepted: 19 June 2007 /Published: 25 June 2007
Abstract: This paper addresses the impact of interconnects imperfections on SNR, INL and DNL of a typical ADC. It is shown that the interconnect-induced jitter reduces SNR up to 25 dB for global interconnects. Considering only the resistance of interconnects, DNL exhibits 3 times dependency more than that of INL. Also a design methodology, based on a stochastic length function, is proposed to find an optimum scheme for clock distribution and to minimize the delay.
Keywords: Interconnect, ADC, Delay, Clock Distribution
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