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Vol. 159, Issue 11, November 2013, pp. 185-189

 

Bullet

 

Design and Application of Counter's Interface IP Core Based on Avalon Bus
 
* Huazhu Wu, Chunguang Zhang, Naihao Luo

Dalian Jiaotong University, Dalian, 116028, China

* Tel.: 86-411-84106961, fax: 86-411-84107613-89

* E-mail: dlwhzh@163.com

 

Received: 15 August 2013   /Accepted: 25 October 2013   /Published: 30 November 2013

Digital Sensors and Sensor Sysstems

 

Abstract: With the wide application of the NIOS II soft-core processor based on FPGA in the control field, the research of the interface IP (intellectual property) core between NIOS II's Avalon bus and peripheral is very valuable. It combines FPGA and realizes the function of encoder pulses' shaping, filtering, frequency multiplication, checking phase, counting and latching in this paper, then it makes use of Verilog language to finish the design of counting model and Avalon bus's interface IP core, finally it takes SOPC (programmable on-chip system) technology to customize the NIOS II soft-core processor. Practical application shows that the design is stable and reliable, it not only can effectively and accurately obtain the pulse signal, and also to simplify the circuit.

 

Keywords: NIOS II soft-core processor, Encoder, FPGA, Avalon bus.

 

 

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