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Vol. 162, Issue 1, January 2014, pp. 117-123

 

Bullet

 

Implementation of Modified FEC Codec and High-Speed Synchronizer in 10G-EPON
 

Min ZHANG, Yue CUI, Qiwang LI, Weiping HAN, Liqian WANG, Mingtao LIU

State Key Laboratory of Information Photonics and Optical Communications Beijing University of Posts and Telecommunications Beijing 100876, China
Tel.: 010-61198087, fax: 010-61198084

E-mail: mzhang@bupt.edu.cn

 

Received: 29 October 2013 /Accepted: 9 January 2014 /Published: 31 January 2014

Digital Sensors and Sensor Sysstems

 

Abstract: This article puts forward parallel forward error correction(FEC) codec for 10 Gb/s Ethernet passive optical network (10G-EPON) , which adopts 8-parallel algorithm based on improved state space transformation (SST) method for Reed-Solomon (RS) encoder and 9-parallel algorithm based on enhanced degree computation-less modified Euclid’s (EDCME) algorithm to solve the key equation for RS decoder. The designed 10 Gb/s codec and high-speed synchronizer are implemented with Verilog HDL on Xilinx FPGA ML523. The implementation results show that, with the high-speed synchronizer, the RS (255, 223) encoder and decoder are able to operate at 15.232 Gb/s and 13.2 Gb/s respectively with shorter time latency than those of the reported designs.

 

Keywords: Parallel FEC, Reed-Solomon, High-speed synchronizer, Pipelining registers, 10G-EPON, FPGA.

 

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