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Vol. 163, Issue 1, January 2014, pp. 128-134

 

Bullet

 

Validation of a Real-time AVS Encoder on FPGA
 

1 Qun Fang Yuan, 2 Xin Liu, 3 Yao Li Wang

1 Student Recruitment and Work Placement Office, Taiyuan University of Technology, Taiyuan, 030024, China
2, 3 College of Information Engineering, Taiyuan University of Technology, Taiyuan, 030024, China
3 Tel.: 00863516010042, fax: 00863516010042

3 E-mail: willingwan@gmail.com

 

Received: 12 November 2013 /Accepted: 12 December 2013 /Published: 31 January 2014

Digital Sensors and Sensor Sysstems

 

Abstract: A whole I frame AVS real-time video encoder is designed and implemented on FPGA platform in this paper. The system uses the structure of the flow calculation, coupled with a dual-port RAM memory between/among the various functional modules. Reusable design and pipeline design are used to optimize various encoding module and to ensure the efficient operation of the pipeline. Through the simulation of ISE software and the verification of Xilinx Vritex-4 pro platform, it can be seen that the highest working frequency can be up to 110 MHz, meeting the requirements of the whole I frame real- time encoding of AVS in CIF resolution.

 

Keywords: AVS, Encoder, FPGA.

 

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