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Vol. 171, Issue 5, May 2014, pp. 86-92

 

Bullet

 

Silicon-on-Insulator Lateral-Insulated-Gate-Bipolar-Transistor with Built-in Self-anti-ESD Diode
 

1 Xiaojun Cheng, 1* Haipeng Zhang, 2 Ruisheng Qi, 3 Buchun Su, 3 Weili Zhao, 4 Dejun Wang

1 School of Electronics & Information, Hangzhou Dianzi University, Hangzhou, 310018, China
2 Shanghai Huali Microelectronics Corporation, Shanghai, 201203, China
3 Grace Semiconductor Manufacturing Corporation, Shanghai, 201203, China
4 School of Electronic Science and Technology, Dalian University of Technology, Dalian, 11602, China
1* Tel.: +86-13093725207, fax: +86-571-86878618

* E-mail: islotus@163.com

 

Received: 11 March 2014 /Accepted: 30 April 2014 /Published: 31 May 2014

Digital Sensors and Sensor Sysstems

 

Abstract: Power SOI (Silicon-On-Insulator) devices have an inherent sandwich structure of MOS (Metal-Oxide-Semiconductor) gate which is very easy to suffer ESD (Electro-Static Discharge) overstress. To solve this reliability problem, studies on design and modification of a built-in self-anti-ESD diode for a preliminarily optimized high voltage SOI LIGBT (Lateral-Insulated-Gate-Bipolar-Transistor) were carried out on the Silvaco TCAD (Technology-Computer-Aided-Design) platform. According to the constrains of the technological process, the new introduction of the N+ doped region into P-well region that form the built-in self-anti-ESD diode should be done together with the doping of source under the same mask. The modifications were done by adjusting the vertical impurity profile in P-well into retrograde distribution and designing a cathode plate with a proper length to cover the forward depletion terminal and make sure that the thickness of the cathode plate is the same as that of the gate plate. The simulation results indicate that the modified device structure is compatible with the original one in process and design, the breakdown voltage margin of the former was expanded properly, and both the transient cathode voltages are clamped low enough very quickly. Therefore, the design and optimization results of the modified device structure of the built-in self-anti-ESD diode for the given SOI LIGBT meet the given requirements.

 

Keywords: Power SOI LIGBT, Built-in self-anti-ESD, Design and modification, Breakdown, Transient time.

 

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