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Vol. 213, Issue 6, June 2017, pp. 30-37




Comparative Analysis of Shift Registers in Different Nanometer Technologies

Rajesh MEHRA, Ayushi GAGNEJA and Priya KAUSHAL

NITTTR Chandigarh, 160019, India

E-mail: rajeshmehra@yahoo.com, splendid.ayushi@gmail.com, pkaushal2407@gmail.com


Received: 8 May 2017 /Accepted: 8 June 2017 /Published: 30 June 2017

Digital Sensors and Sensor Sysstems


Abstract: In this paper, power and speed efficient registers have been designed using different nanometer technologies. Serial in Serial out (SISO) and Serial in Parallel out (SIPO) shift registers are designed using 180 nm and 90 nm technologies. Both the design are analyzed and compared based on power, delay and power-delay-product (PDP). Present portable real time system demands high performance in terms of speed along with low power consumption. The concept of technology scale down has been used to optimize power and delay in booth designs. The schematic of SISO and SIPO has been developed using Cadence Virtuoso software and analysis has been performed using Analog Design Environment. It has been observed from simulation analysis that 90 nm based SISO design shows an improvement of 68.61 % in power and 54.92 % in delay as compared to 180 nm technology. Likewise SIPO design has shown an improvement of 67.75 % in power and 53.32 % in delay as compared to 180 nm technology.


Keywords: CMOS, Flip Flop, Shift register, SISO, SIPO, VLSI.


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