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Vol. 102, Issue 3, March 2009, pp.10-21

 

 

Bullet

 

IEEE 1451.0-2007 Compatible Smart Sensor Readout with Error Compensation Using FPGA

 

1J. Kamala and 2B. Umamaheswari

1Department of Information and Communication Engineering,

2 Department of Electrical and Electronics Engineering,

Anna University, Chennai 600025, India

E-mail: jkamalaa@annauniv.edu

 

 

Received: 9 February 2009   /Accepted: 24 March 2009   /Published: 31 March 2009

 

Abstract: This paper deals with effective usage of user TEDS for developing smart sensor readout which is suitable to estimate and compensate the disturbances occurring in the system. The system parameters are incorporated along with other transducer data. Appropriate processing capabilities are built in Transducer Interface Module TIM for disturbance estimation and compensation. A Verilog based single chip module of IEEE 1451.0 smart sensor is proposed incorporating the above mentioned features. The architecture enables reliable and smart readout for sensors at low cost for a given application. The programmable nature of the proposed architecture enables wide usage of the smart sensor for various applications.

 

Keywords: Estimator, FPGA, Synthesis, Transducer interface model, Transducer electronic data sheet

 

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