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Vol. 27, Special Issue, May 2014, pp. 347-353

 

Bullet

 

2D Numerical Analysis of Metal/Insulator/Thin Film Silicon Systems for TFT’s Applications: Investigation of Active Layer Properties on Quasi-Static Capacitance
 

1 Hadjira TAYOUB, 1 Asmaa BENSMAIN, 1 Baya ZEBENTOUT, 1 Fatima MAACHOU, 1 Zineb BENAMARA and 2 Tayeb Mohammed-Brahim

1Applied Microelectronic Laboratory, Faculty of Engineering, University of Sidi Bel Abbes, 22000, Algeria
2 IETR-Microelectronics Group, UMR6164, University of Rennes I, 35042, Rennes, France
1 Tel.: 00213 48 55 12 84, fax: 00213 48 55 12 84

E-mail: Hadjira.tayoub@gmail.com

 

Received: 23 December 2013 /Accepted: 12 January 2014 /Published: 26 May 2014

Digital Sensors and Sensor Sysstems

 

Abstract: Thin Film Transistors (TFTs) are used as pixel switching and driving elements in active matrix liquid crystal displays. High quality of active layer on glass substrates associated with low temperatures is necessary for fabricating high performances and long-term reliable TFTs. According to the deposition conditions at low temperatures, the thin silicon layer presents an inhomogeneous structure that consist of a random superposition of grains of different sizes, where grains boundaries parallels and perpendiculars appear containing a high density of states in the energy forbidden gap. The purpose of this work is to study the impact of granular structure of active layer on the electrical behavior of Metal/Insulator/TFS systems. We have developed a 2D-numerical code based on the resolution of Poisson’s equation. The application of gate bias allows to simulate the quasi-static capacitance characteristic C(VG).The effect of intergranular DOS, interface states and grain size on the quasi-static capacitance is investigated.

 

Keywords: Quasi-static capacitance, DOS, 2D-numerical simulation, Grain boundary, Grain size.

 

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