|Sensors Related Ph.D. and D.Sc. Theses|
Asynchronous Analog to Digital Interface: a New Class of Converters
Based on Time Quantization
Author: ALLIER E
Advisor: RENAUDIN M.
Coadvisor: SICARD G.
Thèse de Doctorat INPG, Spécialité Microélectronique
This PhD thesis deals with the development of a new design approach in order to reduce significantly the power consumption of Systems on Chips (SoCs) and Communicating Objects. The goal is to obtain systems only driven by the events contained in the useful signal. In this context, this work is focused on a critical block in such signal processing chains: the Analog to Digital Converter (ADC). Thus, a new family of CANs is described, using both an irregular sampling in time of the analog signal (level crossing sampling) and an asynchronous design (no global clock). This approach places the characteristics of these CANs as the dual case of those of usual Nyquist converters: there is a sampling in amplitude and and quantization in time. The associated theory leads to the development of a general methodology of these converters. Knowing the spectral and statistical characteristics of the analog signal, it allows the designer to determine the optimal design parameters of the ADC, in order to reduce the hardware, its activity and so the power dissipation and the electromagnetic emissions. This method has been used for the design of ADCs, in a CMOS 0,18µm standard technology. The electrical simulations have proved that their Figure of Merit (FoM) is improved by one order of magnitude compared to state-of-the-art Nyquist ADCs. The study of complete systems integrating sensor, analog to digital conversion, and digital processing according to this same method, using asynchronism for the sampling scheme and the design, allows us to affirm that very interesting prospects can be hoped as for the reduction of the power dissipation in SoCs.
Identifiers: Analog to Digital Converters (ADCs). Asynchronous Desogn, Irregular Sampling, Analog Design, Figure of Merit (FoM).
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