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Vol. 10, Special Issue, February 2011, pp.191-205



Fast FPGA Implementation of an Original Impedance Analyser


Abdulrahman HAMED, Etienne TISSERAND, Yves BERVILLER,

Laboratoire d’Instrumentation Electronique de Nancy (LIEN)

Faculty of Sciences, University Henri Poincaré of Nancy – BP 70239

54506 Vandoeuvre les Nancy, France

Tel.: (33) 03 83 68 41 64, fax: (33) 03 83 68 41 53

E-mail: etienne.tisserand@lien.uhp-nancy.fr



Received: 22 October 2010   /Accepted: 11 January 2011   /Published: 8 February 2011


Abstract: This article describes in detail the design and rapid prototyping of an embedded impedance analyzer. The measurement principle is based on the feedback control of the excitation voltage VD during a fast frequency sweeping. This function is carried out by a high precision synthesizer whose output resistance RG is digitally adjustable. Real and imaginary parts of the dipole impedance are determined from RG and the phase of VD. The digital architecture design uses the hardware-in-the-loop simulation in which the dipole is modeled using an RLC parallel circuit and a Butterworth Van Dyke structure. All digital functions are implemented on a Stratix II FPGA board with a 100 MHz frequency clock. The parameters taken into account are the frequency range (0 to 5 MHz), speed and resolution of the analysis and the quality factor of the resonant dipole. To reduce the analysis duration, the frequency sweeping rate is adjusted in real time.


Keywords: Electric impedance, Impedance analyser, FPGA, DDS, Hardware in the loop, Piezo sensor.


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