​ Abstract. With rapidly approaching limits of scale for silicon planar MOSFETs, new device designs have begun to appear as replacements for the present planar technology. The potential new device designs include Double Gate (DG) FETs, FinFETs, Tri-Gate FETs, and Omega-Gate FETs. The motivation for moving from a single-gate MOSFET to the gate-all-around transistor has been the minimisation of short-channel effects and more efficient transfer characteristics through a more intimate control of the conduction channel. However, in the drive for minimisation, along with short- channel effects, another major challenge for the process engineer has been the issue of variability. While the effect of increased gate control and variability has been studied exhaustively, there has been relatively less focus on the effect on variability as we move from a 1-D to a 3-D gate architecture. This paper aims to explore the impact of gate architecture on parametric sensitivity. A comparative analysis of performance parameters such as threshold voltage, sub-threshold slope, ION/IOFF ratio, and ON current across different structural parameters, including gate length, oxide thickness, and dielectric materials, is conducted in this proposed work.

Keyword: Planar MOSFET, JLT, TG-FinFET, DIBL, Subthreshold swing, Switching ratio.

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